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샘플 코드

module test1(input clk, input rst, output reg tx = 1);
    reg [7:0] data;
    reg [15:0] cnt_p;
    reg [15:0] cnt_n;
    reg out_p;
    reg out_n;
    reg [4:0] state;
    parameter rate = 5208;
    assign uart_clk = out_p ^ out_n;
    initial
    begin
        cnt_p = 16'd1;
        cnt_n = 16'd1;
        out_p = 0;
        out_n = 0;
        state = 0;
        tx = 1;
        data = 8'h55;
    end
    always @(posedge clk)
    begin
        cnt_p <= cnt_n + 16'd1;
        if (cnt_n == rate)
        begin
            cnt_p <= 16'd1;
            out_p <= ~out_p;
        end
    end
    always @(negedge clk)
    begin
        cnt_n <= cnt_p + 16'd1;
        if (cnt_p == rate)
        begin
            cnt_n <= 16'd1;
            out_n <= ~out_n;
        end
    end
    always @(posedge uart_clk or negedge rst)
    begin
        if (!rst)
        begin
            state <= 0;
            tx <= 1;
        end
        else
        begin
            if (state == 0)
            begin
                state <= 1;
            end
            else if (state != 0)
            begin
                state <= state + 1;
                if (state == 2)
                begin
                    tx <= 0;
                end
                else if (state > 2 && state <= 10)
                begin
                    tx <= data[state - 3];
                end
                else if (state == 11)
                begin
                    state <= 0;
                    tx <= 1;
                end
            end
        end
    end
endmodule