개요

사진

샘플 코드

module test2(input clk, input rst, output led5, led4, led2);
    reg [26:0] cnt;
    assign led5 = ~cnt[24];
    assign led4 = ~cnt[25];
    assign led2 = ~cnt[26];
    always @(posedge clk, negedge rst)
    begin
        if (~rst)
            cnt <= 'b0;
        else
            cnt <= cnt + 1;
    end
endmodule

testbench

module test;
    reg clk,
        rst;
    test2 t(.clk(clk), .rst(rst), .led5(led5), .led4(led4), .led2(led2));
    initial
    begin
        clk = 0;
        rst = 1;
        #2
            rst = 0;
        #2
            rst = 1;
        #20000
            $finish;
    end
    always
        #1
            clk = ~clk;
    initial
    begin
        $dumpfile("test.vcd");
        $dumpvars(0, test);
    end
endmodule