[VC6] MMX 와 SSE 시리즈 명령 집합 지원 등급 검사 (최고 SSE 4.2)

참고 문헌 - 인텔® 64 and IA-32 Architectures Software Developer’s Manual Volume 2 (2A, 2B & 2C): Instruction Set Reference, A-Z》. December 2011. http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.html 《Intel® Processor Identification and the CPUID Instruction》. January 2011. http://developer.intel.com/content/www/us/en/processors/processor-identification-cpuid-instruction-note.html 《AMD64 Architecture Programmer's Manual Volume 3: General Purpose and System Instructions》. December 2011. http://support.amd.com/us/Processor_TechDocs/24594_APM_v3.pdf 《AMD CPUID Specification》. September 2010. http://support.amd.com/us/Embedded_TechDocs/25481.pdf http://en.wikipedia.org/wiki/CPUID
실행 효과 -
코드 는 다음 과 같 습 니 다 -

// SSE          . simd_sse_level       。
#define SIMD_SSE_NONE	0	//    
#define SIMD_SSE_1	1	// SSE
#define SIMD_SSE_2	2	// SSE2
#define SIMD_SSE_3	3	// SSE3
#define SIMD_SSE_3S	4	// SSSE3
#define SIMD_SSE_41	5	// SSE4.1
#define SIMD_SSE_42	6	// SSE4.2

const char*	simd_sse_names[] = {
	"None",
	"SSE",
	"SSE2",
	"SSE3",
	"SSSE3",
	"SSE4.1",
	"SSE4.2",
};


//     MMX   
BOOL	simd_mmx()
{
	const DWORD	BIT_DX_MMX = 0x00800000;	// bit 23
	DWORD	v_edx;

	// check processor support
	__try 
	{
		_asm 
		{
			mov eax, 1
			cpuid
			mov v_edx, edx
		}
	}
	__except (EXCEPTION_EXECUTE_HANDLER)
	{
		return FALSE;
	}
	if ( v_edx & BIT_DX_MMX )
	{
		// check OS support
		__try 
		{
			_asm
			{
				pxor mm0, mm0	// executing any MMX instruction
				emms
			}
			return TRUE;
		}
		__except (EXCEPTION_EXECUTE_HANDLER)
		{
		}
	}
	return FALSE;
}


//   SSE          
int	simd_sse_level()
{
	const DWORD	BIT_D_SSE = 0x02000000;	// bit 25
	const DWORD	BIT_D_SSE2 = 0x04000000;	// bit 26
	const DWORD	BIT_C_SSE3 = 0x00000001;	// bit 0
	const DWORD	BIT_C_SSSE3 = 0x00000100;	// bit 9
	const DWORD	BIT_C_SSE41 = 0x00080000;	// bit 19
	const DWORD	BIT_C_SSE42 = 0x00100000;	// bit 20
	BYTE	rt = SIMD_SSE_NONE;	// result
	DWORD	v_edx;
	DWORD	v_ecx;

	// check processor support
	__try 
	{
		_asm 
		{
			mov eax, 1
			cpuid
			mov v_edx, edx
			mov v_ecx, ecx
		}
	}
	__except (EXCEPTION_EXECUTE_HANDLER)
	{
		return SIMD_SSE_NONE;
	}
	if ( v_edx & BIT_D_SSE )
	{
		rt = SIMD_SSE_1;
		if ( v_edx & BIT_D_SSE2 )
		{
			rt = SIMD_SSE_2;
			if ( v_ecx & BIT_C_SSE3 )
			{
				rt = SIMD_SSE_3;
				if ( v_ecx & BIT_C_SSSE3 )
				{
					rt = SIMD_SSE_3S;
					if ( v_ecx & BIT_C_SSE41 )
					{
						rt = SIMD_SSE_41;
						if ( v_ecx & BIT_C_SSE42 )
						{
							rt = SIMD_SSE_42;
						}
					}
				}
			}
		}
	}

	// check OS support
	__try 
	{
		_asm
		{
			xorps xmm0, xmm0	// executing any SSE instruction
		}
	}
	__except (EXCEPTION_EXECUTE_HANDLER)
	{
		return SIMD_SSE_NONE;
	}

	return rt;
}

int main(int argc, char* argv[])
{
	int i;
	BOOL	bmmx = simd_mmx();
	int	nsse = simd_sse_level();
	printf("MMX: %d
", bmmx);
	printf("SSE: %d
", nsse);
	for(i=1; i<sizeof(simd_sse_names); ++i)
	{
		if (nsse>=i)	printf("\t%s
", simd_sse_names[i]);
	}

	// wait
	getch();
	printf("
");
	return 0;
}