Systemverilog 관한 필기

그냥 내가 몰랐던거나 햇갈리는 문법들에 대해 적어두려고 한다

1. function automatic

출처: https://sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf

Note that synthesis requires that tasks and functions defined in a package be declared as automatic

function automatic logic is_rs1_fpr (input fu_op op);
    if (FP_PRESENT) begin // makes function static for non-fp case
        unique case (op) inside
            [FMUL:FNMADD],                   // Computational Operations (except ADD/SUB)
            FCVT_F2I,                        // Float-Int Casts
            FCVT_F2F,                        // Float-Float Casts
            FSGNJ,                           // Sign Injections
            FMV_F2X,                         // FPR-GPR Moves
            FCMP,                            // Comparisons
            FCLASS,                          // Classifications
            [VFMIN:VFCPKCD_D] : return 1'b1; // Additional Vectorial FP ops
            default           : return 1'b0; // all other ops
        endcase
    end else
        return 1'b0;
endfunction