【FPGA】【Verilog】【기초 모듈】트리거 & 레지스터

D 트리거:

//D 
module dff(q,clk,data);
	output q;
	input data, clk;
	reg q;

	always @(posedge clk)
		begin
			q  = data;
		end

endmodule 

기본 설정 재설정:
    

module dff2(q, qb, d, clk, set, reset);
	input d, clk, set, reset;
	output q, qb;
	
	reg q, qb;

	always @(posedge clk)
		begin 
			if(reset )
				begin 
					q = 0;
					qb = 1;
				end 
			else 
				if(set )
					begin 
						q  = 1;
						qb = 0;
					end
				else 
					begin 
						q = d ;
						qb = ~d;
					end 
		end 
endmodule 

잠금 레지스터:
    ()?(): () 구현:

// 
module latch1 (q,data ,clk);
output q;
input data ,clk;

assign q = clk? data : q ;

endmodule

    ()?(): () 를 실행하고 비트를 재설정합니다.

// 
module latch2 (q ,data ,clk,set ,reset );
	input data ,clk,set,reset;
	output q;
	
	assign q = reset ? 0 : 
									( set ? 1 : 
													(clk ? data : q  ));
	endmodule 

if 구현:

module latch3(q,data ,clk);
	output q;
	input data ,clk;
	reg q;
	
		always @(clk or data )
			begin
				if(clk)
					q = data ;
			end 
endmodule