【코드】verilog의: 버튼 떨림 제거

/*--------------------------------------------------------------------------------------
-- Filename ﹕ show_ctrl.v
-- Author ﹕tony-ning
-- Description ﹕       
-- Called by ﹕Top module
-- Revision History ﹕15-10-16
-- Revision 1.0
-- Company ﹕ 
-- Copyright(c)  All right reserved
---------------------------------------------------------------------------------------*/

module debounce_module 
(
    CLK, //    ，40Hz
    RSTn, //      
    BUTTON_IN, //      
    BUTTON_OUT //        
);
    input CLK;
    input RSTn;
    input BUTTON_IN;
    output BUTTON_OUT;

    reg key_reg1,key_reg2,key_out;
    reg [24:0]count2;
    
    always @( posedge CLK)//CLK 50M
        begin
        count2<=count2+1;
        if(count2==250000)
        begin
            key_reg1<=BUTTON_IN; 
            count2<=0;
        end
        key_reg2<=key_reg1; 
        key_out<=key_reg2&(!key_reg1); 
     end

    assign BUTTON_OUT = key_out;
    
endmodule

 1 /*--------------------------------------------------------------------------------------
 2 -- Filename ﹕ show_ctrl.v
 3 -- Author ﹕tony-ning
 4 -- Description ﹕      
 5 -- Called by ﹕Top module
 6 -- Revision History ﹕15-10-16
 7 -- Revision 1.0
 8 -- Company ﹕ 
 9 -- Copyright(c)  All right reserved
10 ---------------------------------------------------------------------------------------*/
11 module debounce_module 
12 (
13     CLK, //    ，40Hz
14     RSTn, //      
15     BUTTON_IN, //      
16     BUTTON_OUT //        
17 );
18     input CLK;
19     input RSTn;
20     input BUTTON_IN;
21     output BUTTON_OUT;
22 reg [23:0]cnt;//     
23     reg CLK40HZ;//    
24     reg BUTTON_IN_Q, BUTTON_IN_2Q, BUTTON_IN_3Q;
25     
26     always@(posedge CLK ) //    
27     begin
28         if(!RSTn)  
29             cnt<=0;
30         else if(cnt==24'd312_499)   //  40Hz    
31                 begin
32                 cnt<=0;
33                 CLK40HZ<=~CLK40HZ;//40hz    
34                 end
35             else begin
36                 cnt<=cnt+1;
37                 end
38     end
39     
40     always @(posedge CLK40HZ or negedge RSTn)
41     begin
42         if(~RSTn)
43             begin
44             BUTTON_IN_Q <= 1'b1;
45             BUTTON_IN_2Q <= 1'b1;
46             BUTTON_IN_3Q <= 1'b1;
47             end
48         else
49             begin
50             BUTTON_IN_Q <= BUTTON_IN;
51             BUTTON_IN_2Q <= BUTTON_IN_Q;
52             BUTTON_IN_3Q <= BUTTON_IN_2Q;
53             end
54     end
55     
56     wire BUTTON_OUT = BUTTON_IN_2Q | BUTTON_IN_3Q;
57 endmodule

 1 /*--------------------------------------------------------------------------------------
 2 -- Filename ﹕ show_ctrl.v
 3 -- Author ﹕tony-ning
 4 -- Description ﹕       
 5 -- Called by ﹕Top module
 6 -- Revision History ﹕15-10-16
 7 -- Revision 1.0
 8 -- Company ﹕ 
 9 -- Copyright(c)  All right reserved
10 ---------------------------------------------------------------------------------------*/
11 
12 module debounce_module
13 (
14     CLK, RSTn, KEY_set,KEY_add,Pin_set, Pin_add
15 );
16     
17      input CLK;
18      input RSTn;
19      input KEY_set;
20      input KEY_add;
21      output Pin_set;
22      output Pin_add;
23      
24      reg p=1'b0;//    
25      reg [23:0]cntt;
26      reg k1f1,k1f2;//KEY_set     
27      reg k2f1,k2f2;//KEY_add     
28      
29     
30      parameter s_wait=1'b0;//      
31      parameter s_delay=1'b1;//      
32     
33      assign Pin_set=k1f2&!k1f1;//       
34      assign Pin_add=k2f2&!k2f1;
35      
36      
37      
38      
39      
40     
41      always @ ( posedge CLK or negedge RSTn )//       
42          if( !RSTn )
43               begin
44                   cntt <= 24'd0;
45                   p <= s_wait;
46                 end
47         else case(p)
48             s_wait: begin
49                         k1f1<=KEY_set;//     
50                         k1f2<=k1f1;
51                         
52                         k2f1<=KEY_add;
53                         k2f2<=k2f1;
54                         
55                         if(Pin_set| Pin_add)//   ，                 
56                         begin
57                             p<=s_delay;
58                             k1f1<=0;
59                             k1f2<=0;
60                                   
61                             k2f1<=0;
62                             k2f2<=0;
63                         end
64                     end
65             s_delay:if(cntt==24'd249_999)   //  T=10ms
66                         begin
67                         cntt<=0;
68                         p<=s_wait;
69                         end
70                     else begin
71                         cntt<=cntt+1;
72                         end
73             
74             endcase
75      
76      
77      
78      
79      
80      
81      
82      
83      
84           
85     
86 
87 endmodule